Down-converters in wireless receivers perform a transformation of a radio frequency (RF) signal into a baseband signal centered at zero frequency. In high performance equipment, digital down-converters are used, making it necessary to convert an analog RF signal into a digital signal. Typically, a high-speed ADC is used because of the high frequency of the RF signal.
High speed analog to digital converters are generally built as composite ADCs that consist of a number of time interleaved sub-ADCs with a common input and sequential timing. In general, the amplitude frequency response and phase frequency response of the different sub-ADCs are not identical, resulting in specific signal distortions, for example, the appearance of spurious frequency components. To prevent these distortions, equalization of the responses of the sub-ADCs is used (see, for example, U.S. Pat. No. 7,408,495).
A block diagram of a conventional digital down-converter with an equalizer, is shown in FIG. 1. An RF signal, applied to the input of a composite ADC 1, is transformed into a digital signal. The misalignment of the frequency responses of the sub-ADCs of ADC 1, is corrected by an equalizer 2. An I/Q demodulator is constructed using two mixers 3 and 5 with a common local oscillator frequency ωLO and with a phase difference of 90 degrees. Low pass filters 4 and 6 produce two outputs labeled In-Phase (I) and Quadrature (Q).
The equalizer 2 and the low pass filters (LPFs) 4 and 6 in the block diagram of FIG. 1 are built usually as conventional finite impulse response (FIR) filters. The most resource-consuming components of such FIR filter are multipliers. Because of the difference between the RF signal frequency (typically several GHz) and the frequency of operation of present-day FPGAs (up to 200-250 MHz), each multiplication in the FIR filters is carried out by a group of multipliers connected in parallel. The required number of multipliers becomes the main reason that makes it necessary to use in the equalizer design, more FPGAs and/or FPGAs of larger size or, in some cases, makes the real time equalizer design impossible.
This problem was solved (partially at least) in U.S. Pat. No. 9,148,162; U.S. Pat. No. 9,634,679; and U.S. Pat. No. 9,641,191. In those patents, it was proposed there to combine equalization with down conversion, performing equalization in I and Q branches of the down converter separately. Furthermore, the cascade connected units in each branch (equalizer, low pass filter and, maybe, mixer) are replaced by a single finite impulse response (FIR) filter. A decimator is placed inside the FIR before the multipliers. In that way the frequency of each multiplication in the down converter is lowered and the number of required multipliers is reduced significantly.
That solution, which is proposed in the above-cited patents, makes it possible for the first time to design a digital down converter which operates in a real time mode. However, the full potential for reduction in the number of multipliers is not completely exploited. The equalizers in the above-cited patents are required to correct the frequency responses from zero frequency up to the Nyquist frequency, whereas the bandwidth of the processed signals is much narrower. When the bandwidth of the equalizer operation is made narrower in these prior art approaches, the number of taps in the equalizers is cut down proportionally, with the required number of multipliers being reduced as much. The bandwidth of the equalizer operation may be reduced by placing it after the low pass filters, but since samples at the filter outputs are formed as linear combinations of samples produced by all sub-ADCs, the correction of misalignment of frequency responses in this situation becomes impossible.
A number of approaches for correcting misalignment of frequency responses in digital down-converters have been proposed for simplified composite ADCs consisting of two sub-ADCs. For example, U.S. Pat. No. 9,628,097 by Johannson “Methods and devices for handling channel mismatches of an I/Q down-converted signal and a two-channel TI_ADC” describes procedure for compensating ADC mismatch based on I/Q down-converted signals. However, this procedure requires the generation intermediate “service” signals with over-sampling, and does not address overall equalization required for digital down-conversion. A journal paper by Singh, Epp et. al, “Analysis, Blind Identification, and Correction of Frequency Response Mismatch in Two-Channel Time-Interleaved ADCs' (IEEE Transactions On Microwave Theory and Techniques, Vol. 63, No. 5, May 2015), describes theoretical spectra distortions for an ADC with time-interleaved sub-ADCs, and proposed to use blind mismatch identification of two ADC responses and adaptive filtering for frequency response correction. The method of adaptive equalization is not applicable to real time down-conversion applications since adaptive equalization may have significant time lag and convergence issues, and may require transmission of special pilot signals. Moreover, the adaptive equalization method depends on a transmitted signal and is not applicable for test and measurement applications. A calibrated reference high speed ADC with down-conversion is a requirement for characterization of RF equipment, such as analog up- and down-converters, filters and transmission/receiver antennas.
An object of the present technology is provide a digital down-converter, where the bandwidth of equalizer operation is equal to the bandwidth of the processed signals, while at the same time to correcting misalignment of the frequency responses of the sub-ADCs of a composite ADC.